The present invention relates to a method of fabricating semiconductor device s exhibiting high reliability and superior repeatability. The present invention has particular applicability in fabricating high density, multi-level semiconductor devices with feature dimensions in the deep sub-micron regimne.
As the drive for the continued miniaturization proceeds apace, various issues arise imposing increasing demands for methodology enabling the fabrication of semiconductor devices having high reliability and high circuit speed. As the gate width for transistors decreases to about 0.13 micron and under, and as a gate dielectric layers are reduced to about 11 xc3x85 to 13 xc3x85, various issues arise in front end of line (FEOL) microprocessor device fabrication, particularly when employing a silicon-on-insulator (SOI) substrate on which transistors are formed.
A particular problem stems from the undesirable generation of an overlap capacitance under the gate electrode. Such an overlap capacitance is believed generated by the high temperatures employed to deposit a silicon oxide, e.g., a silicon dioxide layer, by conventional techniques, such as thermal oxidation or low pressure chemical vapor deposition, such as elevated temperatures of 800xc2x0 C. to 1000xc2x0 C. The use of such high deposition temperatures undesirably results in silicon consumption and diffusion of the shallow source drain extensions under the gate electrode to an undesirable degree. Silicon oxide layers are typically deposited at a thickness of about 90 xc3x85 to about 110 xc3x85, e.g., about 100 xc3x85.
Accordingly, there exists a need for methodology enabling the fabrication of highly reliable semiconductor devices with high circuit speed, particularly semiconductor devices with transistors formed on SOI substrates. There exists a particular need for methodology enabling the deposition of an ultra thin silicon oxide layer over a gate electrode to form silicon oxide sidewall spacers at a reduced thickness, such as at about 50 xc3x85 or less, with superior within wafer uniformity, excellent step coverage and excellent repeatability from wafer to wafer.
An advantage of the present invention is a method of manufacturing a semiconductor device having improved reliability.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising transistors with reduced overlap capacitance, particularly transistors formed on SOI substrates.
A further advantage of the present invention is a method of manufacturing a semiconductor device comprising depositing a silicon dioxide layer over a gate electrode with improved within water uniformity, improved wafer-to-wafer uniformity, high step coverage and reduced pinholes.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method manufacturing a semiconductor device, the method comprising depositing a layer of silicon oxide at a total thickness of 50 xc3x85 or less in a plurality of deposition stages, each stage comprising depositing a sub-layer of silicon oxide by plasma enhanced chemical vapor deposition (PECVD).
Embodiments of the present invention comprise depositing a layer of silicon dioxide in at least four stages, e.g., five stages, each stage conducted at a reduced deposition rate of about 540 xc3x85/minute or less at a temperature of about 400xc2x0 C. to about 450xc2x0 C. Embodiments of the present invention further include depositing a layer of silicon oxide at a total thickness of about 50 xc3x85 or less, e.g., about 40 xc3x85 or less, in a plurality of deposition stages, each deposition stage comprising depositing a sub-layer of silicon dioxide at a thickness of about 6 xc3x85 to about 10 xc3x85.
Further embodiments of the present invention comprise forming a gate electrode over a substrate, such as an SOI substrate, with a gate dielectric layer therebetween, ion implanting impurities to form shallow source/drain extensions, depositing a layer of silicon dioxide in a plurality of stages at a temperature of about 400xc2x0 C. to about 450xc2x0 C., etching to form silicon dioxide sidewall spacers on side surfaces of the gate electrode, the silicon dioxide sidewall spacers having a thickness no greater than 50 xc3x85, depositing a layer of silicon nitride in the same deposition apparatus employed for depositing the silicon dioxide layer, etching to form silicon nitride layers on the silicon dioxide sidewall spacers, ion implanting impurities to form moderately or heavily doped source/drain regions, and subsequently annealing to activate the shallow source/drain extensions and source/drain regions.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.